OM in the News: New Product Design Keeps Intel a Generation Ahead

Chapter 5 discusses the critical importance of new product design in OM and the impact it can have in the technology arena. Indeed, as The New York Times (May 4,2011) breaks the news about Intel’s success in a 3-D transistor design, we see how important staying ahead of the fierce competition can be. Breaking away from a design (called the planar transistor) that has been a constant in the chip industry since 1959, Intel has found a way to make smaller, faster, and lower-powered chips.

Its designers are turning from 2-dimensional transistor switches (the basic building block of the information age) to a third dimension to find more room. Intel said yesterday that the new process allows chips to run 37% faster in low voltage applications (like iPhones and iPads), while power consumption drops 50%. 

This exciting news is significant because it means the world’s largest chip maker (see yesterday’s blog about the industry) is not slipping from the pace of doubling the number of transistors etched onto a sliver of silicon every 2 years, a phenomenon known as Moore’s Law. This “law”, named after Intel’s co-founder, has set the computer industry apart from other manufacturing because it continued to improve at an accelerating rate.

Intel currently uses  a photolithographic process to make a chip and the current generation is called a 32 nanometer chip. (By comparison a human red blood cell is 7,500 nanometers in width). “Intel is on track for  22 nanometer manufacturing later this year”, says the scientist in charge of the project. By 2015, the firm is on target to make chips in a 10 nanometer generation.

Being first out with the 3-D chip technology gives Intel a full generation lead over competitors, but it does not guarantee success in a fast-changing consumer products market where “ultra-low power” chips are critical in consumer products.

Discussion questions:

1. Why is Moore’s Law a critical part of the chip industry?

2. What is Intel’s gamble in developing the 3-D chip?